Scalably-Verifiable Sequential Synthesis
نویسندگان
چکیده
This report is a case-study of the synergy between sequential synthesis and verification. Described is an efficient implementation of a sequential synthesis that uses simple induction to detect and merge sequentially-equivalent registers and nodes in a sequential circuit with a given initial state. Since retiming is not performed, state-encoding, scan chains, and test vectors are essentially preserved with minor modifications. Moreover, the synthesis results are guaranteed to be verifiable against the original circuits. Verification uses an inductive prover comparable to that used for synthesis, with the runtime close to that of synthesis. Experiments show that applying the synthesis flow to the largest academic benchmarks reduces both registers and area by more than 30%. Applying the flow to a set of 50 industrial benchmarks ranging in size from 100 to 20K registers shows an average reduction of 32% in registers and 15% in area while preserving the delay. The geometric averages of synthesis and verification runtime on the industrial benchmark set are close to 50 sec and 25 sec, respectively. The implementation is publicly available in the logic synthesis and verification system ABC.
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